Nitin Khatri

Nitin Khatri is a semiconductor verification specialist whose 16+ year career has focused on one of the industry’s highest-consequence disciplines: ensuring complex SoC subsystems behave correctly before silicon reaches the fab. Working across Apple, AMD, Synopsys, and earlier PCIe verification roles, Khatri has built a professional identity around functional correctness, protocol compliance, and coverage-driven validation for memory and high-speed I/O—domains where subtle corner-case defects can translate into catastrophic product risk, delayed tape-outs, or post-silicon instability.

At Apple (Design Verification Engineer since September 2022), Khatri’s work centers on pre-silicon verification of LPDDR-based unified memory subsystems supporting modern SoC/IP platforms. His verification approach is rooted in SystemVerilog and UVM architecture, where he develops test plans, constraint-random stimulus, assertion strategies, monitors, scoreboards, and regression flows to expose protocol-level and microarchitectural edge cases. His scope spans JEDEC standards (LPDDR5/LPDDR6, DDR4/DDR5) and adjacent high-speed interfaces—building confidence that the memory system can sustain the bandwidth, latency, and reliability expectations required by contemporary AI workloads and heterogeneous compute engines. Apple has publicly emphasized the M4 generation’s AI acceleration—highlighting a Neural Engine capable of 38 trillion operations per second (38 TOPS)—a level of capability that intensifies the verification burden on memory bandwidth, coherency, and correctness.

Khatri previously contributed to AMD as an MTS Silicon Design Engineer (December 2018–September 2022), where he verified memory controller IP across multiple processor generations and use cases, including DMA engines and PHY register functionality validated through UVM environments with robust checkers and monitors. This work sits directly in the critical path for modern client processors where integrated graphics and NPUs rely on sustained, predictable memory behavior. AMD’s broader platform direction has increasingly emphasized on-device AI, with public materials describing mobile-class processors integrating dedicated NPUs at up to 50 TOPS—raising the bar for memory and interconnect verification discipline needed to feed those engines reliably.

Earlier, at Synopsys (R&D Engineer, Sr II; September 2011–December 2018), Khatri operated at the “tools that enable the industry” layer—contributing to DDR4/DDR5 Verification IP, including modeling, training algorithm validation (e.g., leveling/training sequences), and complete verification environments across DIMM configurations with data-integrity scoreboarding. This type of work compounds impact: Verification IP is leveraged across many customer programs and product lines, amplifying the effect of high-quality methodology and implementations.

Khatri’s career began with hands-on PCIe verification services (nSys Design System Pvt. Ltd., April 2009–September 2011), where he developed compliance-oriented UVM environments and test suites (including extensive Gen1/Gen2/Gen3 coverage) and worked directly with customers to diagnose and resolve verification findings. Across all phases of his trajectory, his differentiator is consistent: taking specification-heavy, corner-case-rich digital interfaces and converting them into systematic verification strategies that de-risk silicon delivery for products used at global scale.