Sagar Mallik

Sagar Mallik has built a career in one of the most exacting disciplines in modern engineering: the design, timing closure, and implementation of complex semiconductor systems. Over more than two decades in semiconductor design engineering, his work has been anchored in ASIC and SoC implementation, Static Timing Analysis (STA), and RTL-to-GDSII methodologies, with contributions spanning technology nodes from 90nm to 2nm. Across 16 successful tape-outs for companies including Google, Amazon, Nvidia, Marvell, Intel, and NXP, he has helped bring some of the industry’s most advanced silicon products from concept to reality, including cloud-scale AI and machine learning accelerators, high-end GPUs, mobile baseband processors, and multimedia chips. His professional journey reflects a rare combination of technical rigor, design depth, and sustained influence across the semiconductor ecosystem.

At the core of Mallik’s expertise is Static Timing Analysis, a field that sits at the heart of semiconductor reliability, performance, and manufacturability. His technical command includes timing-aware design, deep sub-10nm technology effects, signoff margins, STA methodology, timing closure, DFT architecture, timing constraints development for both functional and test modes, clock domain crossing analysis, metastability and MTBF analysis, and chip-level IO timing methodology. His experience also extends into physical implementation disciplines such as synthesis, DFT insertion, formal verification, floorplanning, placement, clock tree synthesis, ECO implementation, SPEF extraction, SDF and timing model creation, EMIR ECO, and GLS debug support. This range of expertise places him among a class of engineers capable of addressing the full lifecycle of high-performance silicon implementation.

At Google Cloud, where he served as Static Timing Analysis Lead, Mallik worked on some of the most advanced process technologies in the world, including TSMC 3nm and 2nm. His responsibilities included modeling timing margins for STA signoff using parametric on-chip variation, on-die voltage and temperature variation, and device aging models. He also defined signoff settings in Primetime covering wire and distance derates, multi-input switching, crosstalk delay and noise analysis, minimum pulse width and period modeling, DRC, and double switching analysis. In collaboration with RTL teams, he helped model clock speed across multiple power states to support advanced dynamic voltage and frequency scaling (DVFS) for power savings and performance-per-watt optimization. His work also included partnering with DFT teams to define test modes and create timing constraints from scratch, as well as architecting full-chip SoC STA methodologies for dies approaching reticle scale using advanced Synopsys methods such as Hyperscale and Hypergrid.

At Amazon Lab126, Mallik served as the sole STA owner for an entire SoC in TSMC 7nm technology, effectively helping build the product from the ground up. He worked directly with RTL designers and architecture owners to define functional timing constraints, estimate pipelining requirements, and shape network-on-chip implementation and clock frequency planning. He also developed IO timing constraints for interfaces including EMMC, DDR, USB camera, and video IP, integrating them into SoC-level signoff. His collaboration with board teams and DFT teams further enabled accurate IO interface constraints and MBIST integration, demonstrating his ability to manage technical precision across both chip-level and system-level boundaries.

Mallik’s work at Marvell as Principal Engineer and STA Lead illustrates another dimension of his technical leadership. There, he led SoC-level timing signoff for SERDES interfaces in TSMC 5nm technology, supporting up to ten SERDES devices for PCIe, Ethernet, and Nokia CPRI protocols. His responsibilities included STA constraints setup, coordination with place-and-route and floorplanning teams, and top-level clock tree routing and PLL placement planning. He also led STA and PNR teams for SERDES block RTL-to-GDSII timing closure, innovating in clock tree synthesis methodologies in the presence of DFT logic. Among his notable contributions was the invention of a flow for placement of pipeline logic in high latency-limited channel designs, using extracted layer velocities for TSMC 7nm and 5nm technologies—an algorithmic advance beyond standard CAD tool capabilities.

Earlier roles at Nvidia, Intel, and NXP further demonstrate the breadth and continuity of his impact. At Nvidia, he worked on the Tegra clocks team and on top-level timing closure methodology for the Kepler GPU series, including crosstalk analysis and runtime optimization for a 680 mm² four-core processor. At Intel IoT and AI, he focused on SoC-level STA, synthesis, and PNR for edge AI wearable devices and also led physical design and STA signoff for 16nm AI inference IP. At NXP Semiconductors, he served as Senior Technical Lead for digital TV SoC timing analysis and contributed to projects in car radar and intelligent traffic systems, including mixed-signal STA flow establishment and FPGA-based R&D integration. Across these roles, his work has repeatedly intersected with major technology trends in AI, communications, multimedia, and automotive systems.

Mallik’s record is also distinguished by external and organizational recognition. At Google, he received the company’s highest performance rating, Transformative Impact “T,” awarded to only the top 4% of employees. His intellectual property contributions include a defensive publication on Technical Commons titled “Eliminating Stuck At Capture Mode in Static Timing Analysis by design,” a novel methodology that reduces compute resources and time to tape-out. He also has a patent filing in process based on his work at Google, and his innovation at NXP resulted in a trade secret on improved transition propagation in STA. In addition, he has contributed to the broader body of semiconductor knowledge through IEEE VDAT 2010 and Cadence Live presentations. These achievements reflect not only technical depth, but peer-level recognition of his contributions to the field.

Beyond technical execution, Mallik’s work shows a sustained commitment to collaboration and knowledge sharing. Throughout his career, he has worked closely with RTL, DFT, physical design, board, and architecture teams, helping align diverse engineering groups around timing closure, performance targets, and design reliability. This collaborative dimension is especially important in semiconductor design, where success depends not only on individual expertise but on cross-functional integration at the highest levels of precision.

For IICSPA Fellowship consideration, Sagar Mallik presents a compelling profile defined by deep technical mastery, original contribution to semiconductor performance engineering, sustained leadership across world-class organizations, and measurable impact on advanced silicon products at global scale. His work reflects the level of professional distinction and field-shaping contribution expected of a fellowship-level candidate.